0 – July. 1. Qualification Package. AT89C51ED2. FLASH 8-bit C51 Microcontroller. 64 Kbytes FLASH, 2 Kbytes EEPROM. AT89C51RD2 / AT89C51ED2. AT89C51ED2-SLSUM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 64kB Flash B RAM VV datasheet, inventory, & pricing. AT89C51ED2-SLSIM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 80C31 w/4k datasheet, inventory, & pricing.
|Published (Last):||4 August 2007|
|PDF File Size:||18.85 Mb|
|ePub File Size:||7.17 Mb|
|Price:||Free* [*Free Regsitration Required]|
AT89C51ED2 Microcontroller Datasheet
This output type can be used as both an input and output without the need to reconfigure the port. If the program counter ever goes astray, a match will eventually occur and cause an internal reset.
Page 54 Table Set to enable KBF. Page 42 Table It is driven by the Master for eight clock cycles which allows to exchange one Byte on the serial lines. Cleared to select 6 clock periods per peripheral clock cycle.
Clear to select 6 clock periods per peripheral clock cycle. All other vectors addresses are the same as standard C52 devices. Figure gives a logical view of the above statements. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set e.
It is based on 8 inputs with programmable interrupt capability dataxheet both high or low level. In this mode, program execution halts. The command “Program Software Security Bit” can only write a higher priority level. When the communication is initialized, the protocol depends on the record type requested by the host.
What’s missing? Tell us about it.
The external CEX input for the datashedt on port 1 is sampled for a transition. Note that one ALE pulse is skipped during each access to external data memory.
Page 32 It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. It contains 64K bytes of program memory organized respectively in pages of bytes. Page 18 Figure Output pulse for latching the low byte of the address during an access to att89c51ed2 memory. Document Revision History Set to configure the SPI as a Master.
Symbol Description Symbol Table Page datashert continue for a number of clock cycles before the internal reset algorithm takes control. Set by hardware when VCC rises from 0 to its nominal voltage.
Page 44 Figure When the pin is pulled low, it is driven strongly and able to sink a fairly large current. Page 58 Table Set to enable SPI interrupt. Page 52 Table This can be useful at889c51ed2 external peripherals are mapped at addresses already used by the internal XRAM.
Can not be set or cleared by software. Power-Down mode stops the oscillator, freezes all clock at known states. PCA at89c51ee2 enable bit Cleared to disable. Its advantages include reduced software overhead and improved accuracy. Page 46 Figure Page 56 Table It contains a Kbyte Flash memory block for code and for data.
The four segments are: The Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. These modes are detailed in the following sections. Save and disable interrupts.
AT89C51ED2 – Microcontrollers and Processors – Microcontrollers and Processors
Set by hardware to indicate that the SS pin is at inappropriate logic level. Page 10 NIC P2. Page 62 Table Set af89c51ed2 enable timer 2 overflow interrupt. Watchdog timers are fatasheet for systems that are susceptible to noise, power glitches, or electrostatic discharge. CF may be set by either hardware or software but can only be cleared by software. Page 76 Table Set to select 12 clock periods per peripheral clock cycle.